The present invention generally relates to the preparation of a semiconductor material substrate, especially a silicon wafer, which is suitable for used in the manufacture of electronic components. More particularly, the present invention relates to a silicon wafer, and a process for the preparation thereof, which has a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further relates to a silicon on insulator structure derived from such a wafer.
Single crystal silicon, which is the starting material for most processes for the fabrication of semiconductor electronic components, is commonly prepared with the so-called Czochralski (CZ) process wherein a single seed crystal is immersed into molten silicon and then grown by slow extraction. Molten silicon is contaminated with various impurities, among which is mainly oxygen, during the time it is contained in a quartz crucible. At the temperature of the silicon molten mass, oxygen comes into the crystal lattice until it reaches a concentration determined by the solubility of oxygen in silicon at the temperature of the molten mass and by the actual segregation coefficient of oxygen in the solidified silicon. Such concentrations are greater than the solubility of oxygen in solid silicon at temperatures typical for the processes for the fabrication of electronic devices. As the crystal grows from the molten mass and cools, therefore, the solubility of oxygen in it decreases rapidly, whereby in the remaining slices or wafers, oxygen is present in supersaturated concentrations.
Thermal treatment cycles which are typically employed in the electronic device manufacturing processes can cause the precipitation of oxygen in silicon wafers which are supersaturated in oxygen. Depending upon their location in the wafer and their relative size, the precipitates can be harmful or beneficial. Small oxygen clusters are electrically active thermal donors and can reduce resistivity regardless of location in the wafer. Large oxygen precipitates located in the active device region of the wafer can impair the operation of the device but when located in the bulk of the wafer, however, are capable of trapping undesired metal impurities that may come into contact with the wafer during, for example, device fabrication processes. This is commonly referred to as internal or intrinsic gettering (“IG”).
Certain applications, such as advanced wireless communication applications, require silicon wafers of relatively high resistivity. For example, conventional advanced wireless communication applications require silicon wafers having a resistivity of greater than 100 ohm cm, and certain advanced applications require resistivities of greater than about 1000 ohm cm. Traditionally, silicon grown by the floating zone (FZ) method has been used for high resistivity applications instead of silicon grown by the Czochralski (CZ) method because of its inherent higher purity. In addition, the relatively high levels of Oi present in CZ silicon, typically in the range of 10–15 parts per million atomic or “ppma,” can be problematic. Although the presence of interstitial oxygen can be beneficial for intrinsic gettering purposes, the formation of electrically active thermal donors in the device layer, due to the agglomeration of interstitial oxygen into small clusters in the temperature range of 300–500° C. (temperatures commonly employed in device manufacturing processes), can be a major problem for high resistivity applications since the final steps of device processing involves the formation of alloys between the metal layers and silicon in this temperature range. Resistivity may be negatively impacted by small oxygen clusters located in the active device region, as well as in the wafer bulk. Conversely, the formation of relatively large oxygen clusters in the wafer bulk at temperatures greater than about 500° C. can be beneficial because the large precipitates do not significantly degrade wafer resistivity, and can provide a site for internal gettering.
The formation of thermal donors is generally not problematic in low resistivity wafers because the residence time in the 300–500° C. temperature range is relatively short (typically about one to two hours), and the majority carriers, introduced in n-type or p-type doping, will normally dominate. For high resistivity applications where the added dopant concentration is low, however, the formation of thermal donors in the device processing steps is a major factor in final wafer resistivity. (See, e.g., W. Kaiser et al, Phys. Rev., 105, 1751, (1957), W. Kaiser et al, Phys. Rev., 112, 1546, (1958), Londos et al Appl. Phys. Lett., 62, 1525, 1993.) Thus, for high resistivity CZ applications, residual interstitial oxygen concentration will strongly influence the rate of thermal donor formation during device processing. For example, a wafer having an initial resistivity of about 1000 ohm cm (p-type) and a residual interstitial oxygen concentration of about 13 parts per million atomic (“PPMA”) immediately prior to the final low temperature alloy sintering steps will, after typical alloy sintering conditions of about 450° C. for about one hour, form about 1014 cm−3 thermal donors. The resistivity of the wafer would first increase and then “flip” to n-type as thermal donors are generated, assuming that each thermal donor generated behaves as a double donor. (See, e.g., M. Claybourn and R. C. Newman; Appl. Phys. Lett., 52, 2139, 1988.) As a result, the final resistivity of the wafer is approximately two orders of magnitude less than the initial resistivity. Conversely, if the initial interstitial oxygen concentration was only about 5 PPMA, the thermal donor concentration after the same 450° C., one hour, anneal would be about 2×1012 cm−3 and the resistivity would remain at about 1000 ohm cm.
Abe et al. reported a process for the preparation of high resistivity CZ crystals. (See, e.g., Electrochemical Society Proceedings, vol. 2000-17, 491–500.) In the reported process, CZ crystals were annealed at 650° C. for 2 hours for oxygen nucleation, then at 800° C. for 4 hours for nucleation growth, and then at 1000° C. for 16 hours for oxygen precipitation. Such long periods and associated expense can be prohibitive. Furthermore, this process was reported to be ineffective for crystals with oxygen concentrations of less than about 16 ppma. It is also known that the nucleation rate at 650° C. is strongly influenced by the initial oxygen concentration and therefore the precipitate density is likely to vary from wafer to wafer. In addition, it is likely that pre-existing oxygen precipitates formed during crystal growth will grow during the 4 hr 800° C.+16 hr 1000° C. anneal. This is the so called “thermal history effect” which requires elimination by subjecting the wafers to an additional high temperature anneal thus adding additional complexity and cost to the process.
Accordingly, a need exists for a silicon wafer, and an efficient and reliable process for the preparation thereof, which is capable of internal getting and which has a high resistivity denuded zone, the denuded zone therefore not being capable of forming thermal donors in an amount to appreciably affect the resistivity thereof when subjected to a semiconductor device manufacturing process. Such a wafer would be suited for a number of different applications, include the preparation of high resistivity silicon on insulator devices.